#include "msp430x14x.h" ;****************************************************************************** ; MSP-FET430P140 - Power Up sequencing of voltage rails. ; Name Seq_rails_timerA1 ; ; Control Method = Timing ; ; Description: ; This program will provide control and monitoring signals for the powering up and down ; of 3 voltage rails based on a timed sequence. ; The power supplies are three low dropout regulators, LDO's, TPS725xx, which have active ; HIGH enables. ; P1.1, P1.2 ,P1.3 provide the enable signals. ; P1.5, P1.6, P1.7 are inputs for monitoring the output voltage. ; P1.0 is the shutdown input ; P1.4 provides a system Reset ; Timer_A is used in the Up mode. ; ; SMCLK = MCLK = TACLK = default DCO ~ 800kHz, therefore base tick is appro. 1.25usec. Exact time not critical. ; To get time interval multiple CCR0 value by 1.25uSec. ; ; ; ; ; MSP430F149 ; --------------- ; | | ; | P1.1 |13----> Control Regulator #3 3.3V ; | | ; | P1.2 |14----> Control Regulator #1 1.8 V ; | | ; | P1.3 |15----> Control Regulator #2 2.5V ; | | ; | P1.7 |19----< Reset from Regulator #2 ; | | ; | P1.5 |17----< Reset from Regulator #1 ; | | ; | P1.6 |18----< Output Regulator #3 ; | | ; | P1.4 |16---> System RESET ; | | ; | P1.0 |12---< Powerdown ; ; ; Joe Di Bartolomeo ; Texas Instruments, Inc ; July , 2002 ;****************************************************************************** ;------------------------------------------------------------------------------ main ORG 01100h ; Program Start ;------------------------------------------------------------------------------ RESET mov #0A00h,SP ; Initialize F149 stackpointer StopWDT mov #WDTPW+WDTHOLD,&WDTCTL ; Stop watchdog ;************************************************************************************************* SetupP1 bis.b #01Eh,&P1DIR ; Port 1 OUTPUTS( 1,2,3,4) INPUTS(0,5,6,7) mov.b #000h, &P1OUT ; Insure P1.1,P1.2 and P1.3 are LOW on start up. ; SYSTEM RESET P1.4 LOW Timer_Setup mov.w #TASSEL1+TACLR,&TACTL ; SMCLK, Clear TAR mov.w #0020h,&CCTL0 ; Timer A in UP mode ;Enable Rail #1 mov.w #4000,&CCR0 ; Load time interval for rail #1 bis.w #MC0,&TACTL ; Start Timer_A in UP mode Wait1 bit.w #0001h,&TACTL ; Wait for power up time to be compete jeq Wait1 xor.b #004h, &P1OUT ; Turn on Rail #1 bic.w #MC0,&TACTL ; Turnoff Timer_A. ;Enable Rail #2 mov.w #TASSEL1+TACLR,&TACTL ; SMCLK, Clear TAR mov.w #3000,&CCR0 ; Load time interval for rail #2 bis.w #MC0,&TACTL ; Start Timer_A in UP mode Wait2 bit.w #0001h,&TACTL ; Wait for power up time to be compete jeq Wait2 xor.b #08h, &P1OUT ; Turn on Rail #2 bic.w #MC0,&TACTL ; Turnoff Timer_A. ;Enable Rail #3 mov.w #TASSEL1+TACLR,&TACTL ; SMCLK, Clear TAR mov.w #3500,&CCR0 ; Load time interval for rail #3 bis.w #MC0,&TACTL ; Start Timer_A in UP mode Wait3 bit.w #0001h,&TACTL ; Wait for power up time to be compete jeq Wait3 xor.b #02h, &P1OUT ;Turn on Rail #3 ; At this point all Regulators are enabled mov.w #6,R14 ; However, need to wait to insure the Resets pins L1 ; are in the proper state, in this case HIGH. mov.w #60000,R15 ; This delay is not needed if Regulators have power good L2 dec.w R15 ; rather than a reset jnz L2 dec.w R14 jnz L1 SYSTEM_RESET bit.b #080h,&P1IN ; All three LDO Reset lines should be High jeq Error ; if not enter Error routine. bit.b #040h,&P1IN ; Should be High jeq Error bit.b #020h,&P1IN ; Should be High jeq Error ; All regulators are enabled and mov.w #6,R14 ; their RESET pins are high, meaning their outputs are OK. L3 ; This delay is the System RESET delay mov.w #60000,R15 L4 dec.w R15 jnz L4 dec.w R14 jnz L3 xor.b #010h, &P1OUT ; Take System Reset High, SYSTEM RESET. Monitor ; Monitor LDO reset lines for drop in voltage. bit.b #080h,&P1IN ; Should be High jnc Error bit.b #040h,&P1IN ; Should be High jnc Error bit.b #020h,&P1IN ; Should be High jnc Error bit.b #01h,&P1IN ; A low on this input signals the MSP430 to powerdown. jnc Powerdown ; Normal operation should be High, If Low enter power down. br #Monitor Error ; An error handler would be placed here which would be nop ; application dependent Powerdown bic.w #MC0,&TACTL ; Turnoff Timer_A. ;Powerdown rail #1 mov.w #TASSEL1+TACLR,&TACTL ; SMCLK, Clear TAR mov.w #4000,&CCR0 ; Load time interval for rail #1 bis.w #MC0,&TACTL ; Start Timer_A in UP mode Wait4 bit.w #0001h,&TACTL ; Wait for power down time to be compete jeq Wait4 xor.b #004h, &P1OUT ; Turn off Rail #1 bic.w #MC0,&TACTL ; Turnoff Timer_A. ;Powerdown rail #2 mov.w #TASSEL1+TACLR,&TACTL ; SMCLK, Clear TAR mov.w #3000,&CCR0 ; Load time interval for rail #2 bis.w #MC0,&TACTL ; Start Timer_A in UP mode Wait5 bit.w #0001h,&TACTL ; Wait for power down time to be compete jeq Wait5 xor.b #08h, &P1OUT ; Turn off Rail #2 bic.w #MC0,&TACTL ; Turnoff Timer_A. ;Powerdown rail #3 mov.w #TASSEL1+TACLR,&TACTL ; SMCLK, Clear TAR mov.w #3500,&CCR0 ; Load time interval for rail #3 bis.w #MC0,&TACTL ; Start Timer_A in UP mode Wait6 bit.w #0001h,&TACTL ; Wait for power down time to be compete jeq Wait6 xor.b #02h, &P1OUT ; Turn off Rail #1 xor.b #010h, &P1OUT ; Take System Reset low, (optional) Stay nop ;Required only for C-spy jmp Stay ;single step ;------------------------------------------------------------------------------ ; Interrupt Vectors ;------------------------------------------------------------------------------ ORG 0FFFEh ; MSP430 RESET Vector DW RESET ; END