[[[DI_3773_LISTING_2]]] #define FS_Val 4095 static int Sin_tab[40] = { 0.500*FS_Val, 0.598*FS_Val, 0.691*FS_Val, 0.778*FS_Val, 0.854*FS_Val, 0.916*FS_Val, 0.962*FS_Val, 0.990*FS_Val, 1.000*FS_Val, 0.990*FS_Val, 0.962*FS_Val, 0.916*FS_Val, 0.854*FS_Val, 0.778*FS_Val, 0.691*FS_Val, 0.598*FS_Val, 0.500*FS_Val, 0.402*FS_Val, 0.309*FS_Val, 0.222*FS_Val, 0.146*FS_Val, 0.084*FS_Val, 0.038*FS_Val, 0.010*FS_Val, 0.000*FS_Val, 0.010*FS_Val, 0.038*FS_Val, 0.084*FS_Val, 0.146*FS_Val, 0.222*FS_Val, 0.309*FS_Val, 0.402*FS_Val, 0.500*FS_Val, 0.598*FS_Val, 0.691*FS_Val, 0.778*FS_Val, 0.854*FS_Val, 0.916*FS_Val, 0.962*FS_Val, 0.990*FS_Val }; void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT ADC12CTL0 = REF2_5V + REFON; // Internal 2.5V ref //Setup DMA triggers for both DMA channels DMACTL0 = DMA0TSEL_5 + DMA1TSEL_5; // DAC12IFG trigger // Setup DMA0 DMA0SA = (int) Sin_tab; // Source block address DMA0DA = DAC12_0DAT_; // Destination single address DMA0SZ = 0x20; // Block size DMA0CTL = DMADT_4 + DMASRCINCR_3 + DMAEN; // Rpt single ch, inc src, word-word //Setup DAC0 Load with Timer_A, group with DAC1 DAC12_0CTL = DAC12LSEL_2 + DAC12IR + DAC12AMP_2 + DAC12IFG + DAC12ENC + DAC12GRP; //Setup DMA1 DMA1SA = (int) Sin_tab+8; // Source block address DMA1DA = DAC12_1DAT_; // Destination single address DMA1SZ = 0x20; // Block size DMA1CTL = DMADT_4 + DMASRCINCR_3 + DMAEN; // Rpt single ch, inc src, word-word //Setup DAC1 Load with Timer_A DAC12_1CTL = DAC12LSEL_2 + DAC12IR + DAC12AMP_2 + DAC12IFG + DAC12ENC; //Setup Timer_A CCTL1 = OUTMOD_3; // CCR1 set/reset CCR1 = 1; // CCR1 PWM Duty Cycle CCR0 = 3; // Clock period of CCR0 TACTL = TASSEL_1 + MC_1; // ACLK, upmode //Turn Off CPU forever LPM3; } [[[END_DI_3773_LISTING_2]]]