di3245l2.txt
;*****************************************************************************
;
; LISTING 2
;
; "Simple emulator speeds testing," EDN, September 25, 2003, pg 67
;
;*****************************************************************************
/* -----------------------------------------------------------------*/
/* CPLD for Emulator 			                              */
/* -----------------------------------------------------------------*/
/* This verilog code instanciates three	                       */
/* 16 bit shift registers and a set of                              */
/* 16 Tri-state buffers			                       */ 
/* -----------------------------------------------------------------*/

module  emulcpld (

	addpin,
	datapino,
	dir,
	addclk,
	dataclko,
	dataclki,
	add,
	datapini,
	len,
	data );


input addpin;		// serial address from microcontroller 
input datapino;	// serial data from microcontroller 
input dir;		// tristate buff enable pin (low = tristate) 
input len;		// latch enable active low 

input addclk;		// serial address from microcontroller clock 
input dataclko;	// serial data out from microcontroller clock 
input dataclki;	// serial data in to microcontroller clock 

reg [15:0] addsreg;	// 16 bit address shift reg 
reg [15:0] dataosreg;	// 16 bit data out (from microcontroller) shift reg 
reg [15:0] dataisreg;	// 16 bit data in  (from microcontroller) shift reg 

output [15:0] add;	// emul processor address bus 
output datapini;	// serial data into microcontroller 

wire [15:0] datin;	// ioput input 
wire [15:0] datout;	// ioput output 
wire [15:0] add;	// emul processor address bus 
wire datapini;		// serial data into microcontroller 

inout [15:0] data;	// bi-directional emul processor data bus 



	// address shift reg - shift add in 
	always @(posedge addclk) begin

	   addsreg <= addsreg << 1;
	   addsreg[0] <= addpin;

	end // always 
	assign add[15:0] = addsreg[15:0];


	// datao shift reg - shift data in 
	always @(posedge dataclko) begin

	   dataosreg <= dataosreg << 1;
	   dataosreg[0] <= datapino;

	end // always 
	assign datout = dataosreg;


	// datai shift reg - shift data out 
	always @(posedge dataclki) begin

	   if (!len) begin
	    dataisreg = datin;
	   end
	   else begin
	    dataisreg <= dataisreg >> 1;
	    dataisreg[15] <= 1;
	   end
	end // always 
	assign datapini = dataisreg[0];


	// i/o buffers for data 
	// input portion 

	assign datin[15:0] = data[15:0];

	// output portion 

	assign data[15:0] = dir ? datout[15:0]:16'bz;


endmodule // emulcpld