di2554l2.txt
;**************************************************************************************************
; LISTING 2 - VERILOG TESTBENCH
; 
; "Gated clock has duty-cycle control," EDN, Aug 17, 2000, pg 132
;
; http://www.ednmag.com/ednmag/reg/2000/08172000/designideas.htm#17di5
;***************************************************************************************************
// ********************************************************************************************
// Filename: pulse_shaper_tb.v
// Author:   Paul Kemp
// Descrip:   Pulse shaper.
//
// Date:     Mon May 8 19:28:29 MST 2000
// ********************************************************************************************

`timescale 1ns/1ps   // 1ns time units with 1ps resolution
`include "pulse_shaper.v"

module pulse_shaper_tb;

//   Register Declarations
reg            CLK;
reg            GATE;
reg            RESET_N;

//   Wire Declarations
wire           PULSE;

//   Testbench Register Variable Declarations
reg            ERROR;       // Error flag to be set when error occurs
reg      [4:0] DECREASE;    //
reg      [4:0] INCREASE;    //
reg      [5:0] count;       //

integer        duty_cycle;  // The duty cycle of the pulse
real           start_time;  // Time the pulse goes high
real           stop_time;   // Time the pulse goes low

// Setup signalscan and timeout
initial begin
  $timeformat(-9, 3, "ns", 6);
  $display("Opening Signalscan vector file");
  $shm_open();
  $shm_probe("AC");
  #(150000) $shm_close();   // Timeout and exit simulation after 150us
  $display ("\n**********************************************************");
  $display ("***  ERROR: Simulation timed out before completion !!  ***");
  $display ("**********************************************************\n");
  $finish;
  end


// Create a 20MHz clock for the pulse shaper
initial
  CLK <= 1'b0;
always
  #25 CLK <= ~CLK;


// Initialize testbench variables and chip signals
initial begin
  DECREASE <= 5'd0;
  INCREASE <= 5'd0;
  GATE <= 1'b0;
		RESET_N <= 1'b0;
  end


// Perform main test
initial begin
  repeat (3) @(posedge CLK);     // Wait for three rising edges of CLK
		#3 RESET_N <= 1'b1;            // Bring serial adder out of reset       
  repeat (2) @(posedge CLK);     // Wait for two rising edges of CLK
  #3 GATE <= 1'b1;
  for (count = 0; count < 21; count = count + 2) begin
    @(negedge CLK);
    #3 INCREASE <= count;
    end
  INCREASE <= 5'd0;
  repeat (2) @(posedge CLK);     // Wait for two rising edges of CLK
  for (count = 0; count < 21; count = count + 2) begin
    @(negedge CLK);
    #3 DECREASE <= count;
    end
  repeat (2) @(posedge CLK);     // Wait for two rising edges of CLK
  #3 GATE <= 1'b0;		
  repeat (3) @(posedge CLK);     // Wait for three rising edges of CLK
  #15 $finish;                   // Exit simulation 15ns after falling edge of CLK
  end

always @(posedge PULSE) begin
  duty_cycle = ((stop_time - start_time) / ($realtime - start_time)) * 100;
  start_time = $realtime;   // Record time pulse goes high
  @(negedge PULSE);
  stop_time = $realtime;    // Record time pulse goes low
  end

pulse_shaper  pulse_shaper
  (
   .CLK(CLK),                    // I
   .GATE(GATE),                  // I
   .GATE_DEC_DLY(GATE_DEC_DLY),  // I
   .GATE_INC_DLY(GATE_INC_DLY),  // I
   .RESET_N(RESET_N),            // I
   .GATE_DEC(GATE_DEC),          // O
   .GATE_INC(GATE_INC),          // O
   .PULSE(PULSE)                 // O
  );

delay_20  delay_20_1
  (
   .IN(GATE_DEC),      // I
   .SELECT(DECREASE),  // I  5 bits
   .OUT(GATE_DEC_DLY)  // O
  );

delay_20  delay_20_2
  (
   .IN(GATE_INC),      // I
   .SELECT(INCREASE),  // I  5 bits
   .OUT(GATE_INC_DLY)  // O
  );

endmodule

module delay_20 
               (
                IN,     // I
                OUT,    // O
                SELECT  // O  5 bits
               );


//   Input Declarations
input       IN;
input [4:0] SELECT;


//   Output Declarations
output      OUT;


//   Register Declarations
reg         OUT;


//   Wire Declarations
wire        TAP_1;   // Tap for 1 ns delay
wire        TAP_2;   // Tap for 2 ns delay
wire        TAP_3;   // Tap for 3 ns delay
wire        TAP_4;   // Tap for 4 ns delay
wire        TAP_5;   // Tap for 5 ns delay
wire        TAP_6;   // Tap for 6 ns delay
wire        TAP_7;   // Tap for 7 ns delay
wire        TAP_8;   // Tap for 8 ns delay
wire        TAP_9;   // Tap for 9 ns delay
wire        TAP_10;  // Tap for 10 ns delay
wire        TAP_11;  // Tap for 11 ns delay
wire        TAP_12;  // Tap for 12 ns delay
wire        TAP_13;  // Tap for 13 ns delay
wire        TAP_14;  // Tap for 14 ns delay
wire        TAP_15;  // Tap for 15 ns delay
wire        TAP_16;  // Tap for 16 ns delay
wire        TAP_17;  // Tap for 17 ns delay
wire        TAP_18;  // Tap for 18 ns delay
wire        TAP_19;  // Tap for 19 ns delay
wire        TAP_20;  // Tap for 20 ns delay

  DLY1	dly1	(.I(IN), .O(TAP_1));
  DLY1	dly2	(.I(TAP_1), .O(TAP_2));
  DLY1	dly3	(.I(TAP_2), .O(TAP_3));
  DLY1	dly4	(.I(TAP_3), .O(TAP_4));
  DLY1	dly5	(.I(TAP_4), .O(TAP_5));
  DLY1	dly6	(.I(TAP_5), .O(TAP_6));
  DLY1	dly7	(.I(TAP_6), .O(TAP_7));
  DLY1	dly8	(.I(TAP_7), .O(TAP_8));
  DLY1	dly9	(.I(TAP_8), .O(TAP_9));
  DLY1	dly10	(.I(TAP_9), .O(TAP_10));
  DLY1	dly11	(.I(TAP_10), .O(TAP_11));
  DLY1	dly12	(.I(TAP_11), .O(TAP_12));
  DLY1	dly13	(.I(TAP_12), .O(TAP_13));
  DLY1	dly14	(.I(TAP_13), .O(TAP_14));
  DLY1	dly15	(.I(TAP_14), .O(TAP_15));
  DLY1	dly16	(.I(TAP_15), .O(TAP_16));
  DLY1	dly17	(.I(TAP_16), .O(TAP_17));
  DLY1	dly18	(.I(TAP_17), .O(TAP_18));
  DLY1	dly19	(.I(TAP_18), .O(TAP_19));
  DLY1	dly20	(.I(TAP_19), .O(TAP_20));

  always @ (IN or SELECT or TAP_1 or TAP_2 or TAP_3 or TAP_4 or TAP_5 or TAP_6 or
            TAP_7 or TAP_8 or TAP_9 or TAP_10 or TAP_11 or TAP_12 or TAP_13 or
	           TAP_14 or TAP_15 or TAP_16 or TAP_17 or TAP_18 or TAP_19 or TAP_20) begin
    case (SELECT)	// synopsys parallel_case
     	5'd0     :	begin
						             OUT = IN;      // No time delay selected
                   end
    		5'd1     :	begin
						             OUT = TAP_1;   // 1 ns delay selected
                   end
    		5'd2     :	begin
						             OUT = TAP_2;   // 2 ns delay selected
                   end
    		5'd3     :	begin
						             OUT = TAP_3;   // 3 ns delay selected
                   end
    		5'd4     :	begin
						             OUT = TAP_4;   // 4 ns delay selected
                   end
    		5'd5     :	begin
						             OUT = TAP_5;   // 5 ns delay selected
                   end
    		5'd6     :	begin
						             OUT = TAP_6;   // 6 ns delay selected
                   end
    		5'd7     :	begin
						             OUT = TAP_7;   // 7 ns delay selected
                   end
    		5'd8     :	begin
						             OUT = TAP_8;   // 8 ns delay selected
                   end
    		5'd9     :	begin
						             OUT = TAP_9;   // 9 ns delay selected
                   end
    		5'd10    :	begin
						             OUT = TAP_10;  // 10 ns delay selected
                   end
    		5'd11    :	begin
						             OUT = TAP_11;  // 11 ns delay selected
                   end
    		5'd12    :	begin
						             OUT = TAP_12;  // 12 ns delay selected
                   end
    		5'd13    :	begin
						             OUT = TAP_13;  // 13 ns delay selected
                   end
    		5'd14    :	begin
						             OUT = TAP_14;  // 14 ns delay selected
                   end
    		5'd15    :	begin
						             OUT = TAP_15;  // 15 ns delay selected
                   end
    		5'd16    :	begin
						             OUT = TAP_16;  // 16 ns delay selected
                   end
    		5'd17    :	begin
						             OUT = TAP_17;  // 17 ns delay selected
                   end
    		5'd18    :	begin
						             OUT = TAP_18;  // 18 ns delay selected
                   end
    		5'd19    :	begin
						             OUT = TAP_19;  // 19 ns delay selected
                   end
     	5'd20    :	begin
						             OUT = TAP_20;  // 20 ns delay selected
                   end
     	default  :	begin
						             OUT = IN;      // No time delay selected
                   end
      endcase
    end

endmodule