di2554l1.txt
;**************************************************************************************************
; LISTING 1 - GATED-CLOCK DUTY-CYCLE CONTROLLER
; 
; "Gated clock has duty-cycle control," EDN, Aug 17, 2000, pg 132
;
; http://www.ednmag.com/ednmag/reg/2000/08172000/designideas.htm#17di5
;***************************************************************************************************

// ********************************************************************************************
// Filename: pulse_shaper.v
// Author:   Paul Kemp
// Descrip:   Gated clock duty cycle controller
//
// Date:     Mon May 8 19:28:29 MST 2000
// ********************************************************************************************

`timescale 1ns/1ps   // 1ns time units with 1ps resolution

module pulse_shaper (
                     CLK,           // I
                     GATE,          // I
                     GATE_DEC_DLY,  // I
                     GATE_INC_DLY,  // I
                     RESET_N,       // I
                     GATE_DEC,      // O
                     GATE_INC,      // O
                     PULSE          // O
                    );

//   Input Declarations
input        CLK;           // System clock
input        GATE;          // Active high signal produces variable duty cycle pulses
input        GATE_DEC_DLY;  // 
input        GATE_INC_DLY;  // 
input        RESET_N;       // Active low asynchronous reset


//   Output Declarations
output       PULSE;         // Variable duty cycle output pulse
output       GATE_DEC;      // 
output       GATE_INC;      // 


//   Register Declarations
reg          GATE_DEC;      // 
reg          GATE_INC;      // 

//   Parameter Declarations
parameter    dly = 1;

// Generate a pulse from the system clock (CLK) and GATE signals. 
assign #dly PULSE = GATE_INC_DLY ^ GATE_DEC_DLY;

always @(posedge CLK or negedge RESET_N or negedge GATE) begin
  if (~RESET_N) begin  
    GATE_INC <= #dly 1'b0;
    end
  else if (~GATE) begin
    GATE_INC <= #dly 1'b0;
    end
  else begin
    GATE_INC <= #dly ~GATE_INC_DLY;
    end
  end

always @(negedge CLK or negedge RESET_N or negedge GATE) begin
  if (~RESET_N) begin  
    GATE_DEC <= #dly 1'b0;
    end
  else if (~GATE) begin
    GATE_DEC <= #dly 1'b0;
    end
  else begin
    GATE_DEC <= #dly ~GATE_DEC_DLY;
    end
  end

endmodule