di2509.txt
;****************************************************************************************************
; LISTING 1 - SOURCE FILE
; 
; "FPGA implements X.50 Division 3 recommendation," EDN, April 13, 2000, pg 199
;
; http://www.ednmag.com/ednmag/reg/2000/041300/designideas.htm#08di1
;****************************************************************************************************

-----------------------------
--    x50.vhd       ------
--    Created by:      ------
--  Andrés Martínez    ------
--   January, 2000     ------
-----------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity x50 is
    port (
        clk: in std_logic;  -- Pulses  of 244 ns width, 125 us Period
        ini: in std_logic;  -- Initialize count
        cuenta: out integer range 0 to 20;  -- Count from 0 to 20
        bit_f: out std_logic;  -- Output bit of X.50 Div3
        itr : out std_logic   --  Pulse in Pos 1 each 125 us
    );
end x50;
architecture x50_arch of x50 is
 
 signal scr: std_logic_vector(6 downto 0);
 signal scr_new: std_logic_vector(6 downto 0);
 signal scr_aux: std_logic_vector(6 downto 0);
 signal aux : std_logic;
 signal count: integer range 0 to 20;
 signal cuenta2: integer range 0 to 20;
begin
-- This process generates the init count when count arrives to 20 
-- Count occurs in  falling edges of pulse clock
 
gen_cuenta:process(clk, ini, aux)
 begin
	if (ini or aux ) = '1' then
		count <= 1;
	elsif clk'event and clk ='1' then
 		if count = 20 then	
			count <= 1;
		else
			count <= count +1;
		end if;
 	end if;
 end process;
gen_dat:process(clk,scr_new)
 begin
    if clk'event and clk = '1' then
 		scr <= scr_new;
 	end if;
 end process;
-- This process generates the polynomial X.50
gen_scr:process(clk, count,scr, aux, ini)
 begin
	if (ini or aux)= '1' then
		scr_new <= "0010110";
	elsif clk'event and clk = '0' then
		for i in 1 to 6 loop
			scr_new(i-1) <= scr(i);
		end loop;
			scr_new(4) <= scr(0) xor scr(3);	
 	end if;
 end process;
-- Process to set the pulse_aux ITR when count arrives to 20
process(clk, count)
 begin
 	if clk'event and clk = '0' then
		if count = 20 then
			aux <= '1';
		else
			aux <= '0';
		end if;
 	end if;
 end process;
 
process(clk, ini)
 begin
	if ini = '1' then
		cuenta2<= 1;
 	elsif clk'event and clk = '1' then
		if cuenta2= 20 then
			cuenta2<= 1;
		else
			cuenta2<= cuenta2+1;
		end if;
	end if;
 end process;
gen_itr:process(cuenta2)
 begin
 	if cuenta2 = 1 then
 		itr <= '1';
 	else
 		itr <= '0';
 	end if;
 end process;
 bit_f <= scr_new(0);
 cuenta <= cuenta2;
 
end x50_arch;