;************************************************************
; Listing 6
;
; "A Verilog programming-language-interface primer,"
; EDN, September 2, 1999, pg 75.
; http://www.ednmag.com/ednmag/reg/090299/18ms525.htm
;************************************************************

module mymodule;
reg [7:0] r1;
initial begin
	r1 = 8'hf;
#100	$invert(r1);	// Invert the content of r1
#100	$finish;
end