;************************************************************
; Listing 4 - Compiled Verilog-XL run with a PLI routine
;
; "A Verilog programming-language-interface primer,"
; EDN, September 2, 1999, pg 75.
; http://www.ednmag.com/ednmag/reg/090299/18ms525.htm
;************************************************************

Compiling source file "test.v"
Highest level modules:
my_module
$print_reg: Value of the reg=10
$print_reg: Value of the reg=3
L9 "test.v": $finish at simulation time 400
15 simulation events