01ms719l4.txt 
;**************************************************************************************************
; LISTING 4 - PHASE-FREQUENCY DETECTOR AND CHARGE-PUMP MODELS
;
; "Simulating mixed-mode designs with Verilog-only models," EDN, Jan 04, 2000, pg 91

; http://www.ednmag.com/ednmag/reg/2001/0101000/01ms719.htm
;
***************************************************************************************************

always @(posedge refclk or posedge reset_updown)
begin
if(reset_updown)
up_w = 0;
else
up_w = 1;
end
always @(posedge fdbkclk or posedge reset_updown)
begin
if (reset_updown)
down_w = 0;
else
down_w = 1;
end
always @(up_w or down_w)
begin
if (up_w & down_w)
begin
#2 reset_updown = 1;
#1 reset_updown = 0;
end
// The real values of the Ir/Ip currents going to the ICO are
// update on the rising edge of the sample clock
always @(posedge ‘SAMPLE_CLK)
begin
chgpmp_ir_out = ‘CHGPMP_IR * (up_val - down_val);
chgpmp_ip_out = ‘CHGPMP_IP * (up_val - down_val);
end