01ms719l3.txt 
;**************************************************************************************************
; LISTING 3 - IR VERILOG MODEL
;
; "Simulating mixed-mode designs with Verilog-only models," EDN, Jan 04, 2000, pg 91

; http://www.ednmag.com/ednmag/reg/2001/0101000/01ms719.htm
;
***************************************************************************************************

initial
begin
vc = 0.0;
vc_prev = 0.0;
filter_ir_out = 0.0;
end
always @(posedge ‘SAMPLE_CLK)
begin
if(pll_pintenable) // if filter is enabled
begin
vc_prev = vc;
filter_ir_out = (‘PLL_SCOPE.IR.chgpmp_ir_out +
(‘FILTER_C3 * ‘SAMPLE_FREQ * (vc_prev - ‘ICO_VREF)))
/ (1.0 + ‘FILTER_C3 * ‘SAMPLE_FREQ * filter_r3_value);
vc = vc_prev +
((‘PLL_SCOPE.IR.chgpmp_ir_out - filter_ir_out) /
(‘FILTER_C3 * ‘SAMPLE_FREQ));
end
end