01ms719l2.txt 
;**************************************************************************************************
; LISTING 2 - IP VERILOG MODEL
;
; "Simulating mixed-mode designs with Verilog-only models," EDN, Jan 04, 2000, pg 91

; http://www.ednmag.com/ednmag/reg/2001/0101000/01ms719.htm
;
***************************************************************************************************

initial
// Voltage va at node should be at ICO_VREF at time 0
va = ‘ICO_VREF;
va_prev = va;
filter_ip_out = 0.0;
filter_cint_value = ‘FILTER_CINT;
end
always @(posedge ‘SAMPLE_CLK)
begin
if(pll_pintenable)
begin
va_prev = va; // assign current value to previous value
va = va_prev + (‘PLL_SCOPE.IR.chgpmp_ip_out /
(filter_cint_value * ‘SAMPLE_FREQ));
filter_ip_out = (va - ‘ICO_VREF)/‘FILTER_RT;
end
end