01ms719l1.txt 
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; LISTING 1 - PARAMETRIC DEFINES FILE
;
; "Simulating mixed-mode designs with Verilog-only models," EDN, Jan 04, 2000, pg 91

; http://www.ednmag.com/ednmag/reg/2001/0101000/01ms719.htm
;
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‘define SAMPLE_FREQ 2.5e9 // Sample Clk Freq. for discrete sim.
‘define VDD_SYN_VAL 3.300 // Synthesizer Supply Voltage
‘define ICO_CK 454.5e-15 // Capacitor in ICO gain circuit
‘define FTOI_C 228e-15 // Capacitor in FTOI circuit
‘define CHGPMP_IR 8.0e-6 // Bias Current in IR Charge Pump
‘define CHGPMP_IP 1.6e-6 // Bias Current in IP Charge Pump
‘define FILTER_C3 10.0e-12 // Capacitor Value in IR Filter circuit
‘define FILTER_R3_FM 132.0e3 // Resistor Value in IR Filter
‘define FILTER_CINT 80.0e-12 // Capacitor Base Value in IP Filter
‘define FILTER_RT 12.0e3 // Resistor Value in IP Filter circuit